The present invention relates to multi-core system-on-a-chip integrated circuits, and more particularly to heterogeneous integrated circuits having both arithmetic cores and programmable bit level logic cores.
Wireless, imaging and broadband communications processing systems commonly use both signal and logical processing operations. Architectures suited to one type of processing are typically not suited or appropriate for the other. General-purpose architectures are limited both in flexibility and efficiency for digital signal processor, DSP, operations. DSP architectures, developed for arithmetic operations, are not optimal in functions with extensive bit level manipulations. Heterogeneous architectures, that is integrated circuits having both types of cores, provide one solution to this tradeoff.
For example, in a wireless communications system, the transmitted signals are normally encoded with error protection codes. When such signals are received, they must first be decoded to recover the transmitted information. Decoding is a bit level process. The decoded or recovered signal is processed by various arithmetic algorithms, e.g. for echo cancellation. Such arithmetic operations are best performed in DSPs.
The tradeoffs are further complicated by the fact that algorithms and standards in many emerging areas of signal processing, especially communications, are evolving. That is, new algorithms are being developed to meet new standards and it is desirable to update systems as soon as possible. In addition, it is desirable that both bit level and DSP processing operations be flexible so that different algorithms may be used for different signal streams which pass through the same system or for the same signal streams at different times. This diversity of processing and need for flexibility and reconfigurability of operation make fully programmable systems attractive to system designers.
In accordance with the present invention, an integrated circuit includes a digital signal processor, at least one programmable logic core, shared memory and a memory bus system coupling the digital signal processor and programmable logic core to the memory and to each other. The bus system provides simplified high-speed data transfer between the programmable logic core and the digital signal processor.
In a preferred embodiment, the integrated circuit includes at least two programmable logic cores. With two programmable logic cores, both preprocessing and post-processing can be provided to accelerate system operation.